The present invention relates to a manufacturing method of a semiconductor device employing an electron beam exposure method in a manufacturing process of super-LSI (large scale integration) or the like.
In super-LSI manufacturing processes, the elements are becoming finer and higher in density. Along with the trend of using higher density elements, the wiring pattern length becomes longer, and the wiring pattern width and space are much finer. Lately, in forming ultrafine resist patterns, an exposure method using electron beam (EB exposure) has been developed and put in practical use.
FIG. 2 shows an example of a conventional multilayer metal wiring pattern process. In particular, to make a fine wiring pattern width, a fine wiring pattern space and fine contact holes, the EB exposure method is employed.
In FIG. 2, numeral 1 denotes a silicon substrate forming an active element. Numeral 2 is a first interlayer dielectric film. Usually, after forming elements such as transistors on the silicon substrate 1, the first interlayer dielectric film 2 is deposited. As the first interlayer dielectric film 2, for example, a BPSG (boron doped phospho-silicate glass) film is used. Numeral 3 denotes a first metal wiring, for example, an aluminum film. Numeral 4 is a second interlayer dielectric film, which is to insulate between the metal wiring pattern 3 and its upper metal wiring. Numeral 6 denotes a resist for EB exposure for etching a via hole (hereinafter the contact hole between metal wirings is called the via hole). Numeral 7 is a via hole for connecting between the metal wiring pattern 3 and its upper metal wiring, and it is formed by dry etching using the resist 6 as the mask. Numeral 8 is a second metal wiring to be connected with the first metal wiring pattern 3 through the via hole 7.
Referring to FIG. 2, the conventional process is explained below. FIG. 2(a) represents a state in which the first interlayer dielectric film 2, metal wiring pattern 3 forming patterns, and second interlayer dielectric film 4 are sequentially deposited on the silicon substrate 1. More specifically, the first interlayer dielectric film 2 made of 1 .mu.m thick BPSG film is deposited on the silicon substrate 1 by using an atmospheric Chemical Vapor Deposition (CVD) apparatus. On its upper layer, a 0.8 .mu.m Al film is deposited, patterned, and etched to form the metal wiring pattern 3. Later, by the plasma CVD (plasma-enhanced chemical vapor deposition) method, a silicon oxide film is deposited to form the second interlayer dielectric film 4 having a film thickness of 2 .mu.m. FIG. 2(b) represents a state in which the resist 6 is applied in order to form a via hole. The resist 6 is a resist for EB exposure. For example, a 1.7 .mu.m thick resist 6 is used. FIG. 2(c) represents a state in which the resist 6 is exposed by the EB method and patterned. FIG. 2(d) represents a state in which the second interlayer dielectric film 4 is dry etched by using the resist 6 as the mask. FIG. 2(e) represents a state after removing the resist 6 and cleaning. FIG. 2(f) represents a state in which the metal for a second metal wiring pattern 8 is formed. An Al film is deposited as the second metal wiring pattern 8. FIG. 2(g) represents a patterning state of the second metal wiring 8.
In this manufacturing method, however, since the EB exposure method is used as the exposure method, "charge-up," due to accumulation of incident electrons in the dielectric film, is a serious problem. "Charge-up" refers to an increase in the negative charge of a layer and occurs when the layer is exposed to electrons, for example by way of the via hole during EB exposure. As a result of charge-up, the pattern may be deviated several microseconds during EB exposure. In particular, when the second interlayer dielectric film 4 is thick, or the resist 6 is thick, it is a serious problem. Moreover, if the elements in the base are floating electrically, for example, in the case of elements in a semiconductor-on-insulator (i.e. SOI) structure, there is no escape route for resident electrons, and the effect of charge-up is significant. If charge-up occurs due to EB exposure, the interlayer dielectric film may be broken due to abnormal discharge in a position which is weak electrically, or the alignment signal may not be obtained in exposure, or the alignment may be largely deviated. Furthermore, damage to elements is a problem.
Furthermore, in dry etching after via hole pattern exposure, the selection ratio of the resist 6 and the second interlayer dielectric film 4 is significant. For example, in dry etching of a silicon oxide film, gas such as CHF.sub.3 /O.sub.2 /N.sub.2 is used, and the selection ratio of the resist 6 and oxide film is about 1.5 to 3. As shown in FIG. 2, when the second interlayer dielectric film 4 is deposited to a thickness of 2 .mu.m on a 0.8 .mu.m thick first metal wiring 3, the second interlayer dielectric film 4 has a step of about 0.8 .mu.m due to the presence of the first metal wiring pattern 3. Therefore, assuming the worst condition when a 1.7 .mu.m thick resist 6 is applied, the applied resist 6 becomes thinnest at the position above the first metal wiring pattern 3, with the thickness at this location of 0.9 .mu.m. Of course, in the positions where the first metal wiring pattern 3 is absent, the thickness is 1.7 .mu.m. Hence, supposing the selection ratio to be 2, in the case of etching of the 2 .mu.m thick second interlayer dielectric film 4, if the over-etching rate is 10%, it is desirable to etch by 2.2 .mu.m as converted to the oxide film, and 1.1 .mu.m of the resist 6 is etched. Therefore, the resist 6 on the second interlayer dielectric film 4 in which the first metal wiring pattern is present is completely etched, and the second interlayer dielectric film 4 beneath the resist 6 is also etched to some extent. This problem occurs when the resist film thickness, dry etching condition, step, or other conditions change. In particular, when etched in the above condition, the second interlayer dielectric film 4 is also etched.